TMS320VC5502 datasheet(170/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-44. HPI Read and Write Switching Characteristics

(1) (2) (3)

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

Case 1. HPIC or HPIA read

K = 1(5)

9 * 2H + 20

Case 2. HPID read with no

K = 2(5)

10 * 2H + 20

auto-increment(4)

K = 4(5)

11 * 2H + 20

Delay time, DS low to HD

td(DSL-HDV)

K = 1(5)

9 * 2H + 20

valid

Case 3. HPID read with

auto-increment and read

K = 2(5)

10 * 2H + 20

FIFO initially empty(4)

K = 4(5)

11 * 2H + 20

Case 4. HPID read with auto-increment and

data previously prefetched into the read FIFO

tdis(DSH-HDV)

Disable time, HD high-impedance from DS high

ten(DSL-HDD)

Enable time, HD driven from DS low

td(DSL-HRDYL)

Delay time, DS low to HRDY low

td(DSH-HRDYL)

Delay time, DS high to HRDY low

K = 1(5)

10 * 2H + 20

Case 1. HPID read with no

K = 2(5)

11 * 2H + 20

auto-increment(4)

K = 4(5)

12 * 2H + 20

Delay time, DS low to HRDY

td(DSL-HRDYH)

high

K = 1(5)

10 * 2H + 20

Case 2. HPID read with

auto-increment and read

K = 2(5)

11 * 2H + 20

FIFO initialy empty(4)

K = 4(5)

12 * 2H + 20

td(HDV-HRDYH)

Delay time, HD valid to HRDY high

td(COH-HINT)

Delay time, CLKOUT high to HINT change(6)

Case 1. HPIA write(4)

K = 1, 2, 4(5)

5 * 2H + 20

K = 1(5)

5 * 2H + 20

Delay time, DS high to HRDY

H34

td(DSH-HRDYH)

Case 2. HPID write with no

high

K = 2(5)

5 * 2H + 20

auto-increment(4)

K = 4(5)

6 * 2H + 20

K = 1(5)

40 * 2H + 20

Delay time, DS low to HRDY high for HPIA write and FIFO

H35

td(DSL-HRDYH)

K = 2(5)

40 * 2H + 20

not empty(4)

K = 4(5)

24 * 2H + 20

H36

td(HASL-HRDYL)

Delay time, HPI.HAS low to HRDY low

(1)

DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0,

HCNTL1, HPI.HBIL, and HR/W.

(2)

H is half the SYSCLK1 clock cycle.

(3)

A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.8, Host-Port Interface (HPI), for

more details.

(4)

Assumes no other DMA or CPU memory activity.

(5)

K = divider ratio between CPU clock and SYSCLK1. For example, when SYSCLK1 is set to the CPU clock divided by four, use K = 4.

(6)

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as

CLKOUT.

Specifications

170

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