TMS320VC5502 datasheet(99/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.14.1.1

XPORT Configuration Register (XCR)

The XPORT Configuration Register bit layout is shown in Figure 3-44 and the bits are described in

Table 3-49.

INTERREN

Reserved

R/W, 1

R, 0000000

Reserved

R, 00000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-44. XPORT Configuration Register Layout (0x0100)

Table 3-49. XPORT Configuration Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

INTERREN

R/W

INTERREN bit

•

INTERREN = 0:

The XPORT will not generate a bus error for invalid accesses to

registers listed in Table 3-48. Note that any invalid accesses to

these registers will hang the pipeline.

•

INTERREN = 1:

The XPORT will generate a bus error for invalid accesses to

registers listed in Table 3-48.(1) Note that when a bus error

occurs, any data returned by the read instruction will not be

valid.

Reserved

14-0

000000000000000

Reserved

(1)

This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed

in idle without the CPU being in idle.

Functional Overview

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