TMS320VC5502 datasheet(59/189 Pages) TI

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Point A

Divider

Point B

PLL Core

Multiplier M1

Divider

OD1

PLLM

PLLDIV0

PLLDIV2

PLLDIV1

CK3SEL

WKEN

OSCDIV1

PLLDIV3

PLLCSR

PLLEN

Point C

Oscillator Power-Down Control

SYSCLK1

SYSCLK2

SYSCLK3

CLKOUT3

OSCOUT

X2/CLKIN

CLKMD0

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Figure 3-14. Clock Generator Registers

3.10.4.1

C55x Subsystem Clock Group

Changes to the PLL Control Register (PLLCSR), the PLL Divider0 Register (PLLDIV0), and the PLL

Multiplier Register (PLLM) affect the clock of this clock group. The following procedure must be followed to

change or to set the PLL to a specific value:

1. Switch to bypass mode by setting the PLLEN bit to 0.

2. Set the PLL to its reset state by setting the PLLRST bit to 1.

3. Change the PLL setting through the PLLM and PLLDIV0 bits.

4. Wait for 1 µs.

5. Release the PLL from its reset state by setting PLLRST to 0.

6. Wait for the PLL to relock by polling the LOCK bit or by setting up a LOCK interrupt.

7. Switch back to PLL mode by setting the PLLEN bit to 1.

The frequency of the C55x Subsystem Clock Group can be up to 300 MHz for the TMS320VC5502-300

and up to 200 MHz for the TMS320VC5502-200.

Functional Overview

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