TMS320VC5502 datasheet(36/189 Pages) TI

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3.1.4

Memory Map

000000h

DARAM0

(8K Bytes)

004000h

008000h

(4M minus 64K Bytes(A,C))

010000h

DARAM1

(8K Bytes)

DARAM2

(8K Bytes)

DARAM3

(8K Bytes)

External CE0 Space

(4M Bytes(C))

External CE1 Space

(4M Bytes(C))

External CE2 Space

(4M minus 32K Bytes(B,C))

External CE3 Space

ROM

(32K Bytes)

FF8000h

C00000h

800000h

400000h

000000h

004000h

008000h

00C000h

010000h

(4M Bytes(C))

External CE1 Space

(4M Bytes(C))

External CE2 Space

(4M Bytes(C))

External CE3 Space

C00000h

800000h

400000h

MPNMC = 0

MPNMC = 1

(4M minus 64K Bytes(A,C))

External CE0 Space

DARAM4

(8K Bytes)

DARAM5

(8K Bytes)

DARAM6

(8K Bytes)

DARAM7

(8K Bytes)

00E000h

00C000h

00A000h

002000h

006000h

DARAM0

(8K Bytes)

DARAM1

(8K Bytes)

DARAM2

(8K Bytes)

DARAM3

(8K Bytes)

DARAM4

(8K Bytes)

DARAM5

(8K Bytes)

DARAM6

(8K Bytes)

DARAM7

(8K Bytes)

00E000h

00A000h

002000h

006000h

(A)

The 64K bytes are the on-chip DARAM block.

(B)

The 32K bytes are for on-chip ROM block.

(C)

The CE space size shown in the figure represents the maximum addressable memory space for a 32-bit EMIF configuration. The

maximum addressable memory space per CE is reduced when 16- or 8-bit EMIF configurations are used for asynchronous and

SBSRAM memory types. For more detailed information, refer to TMS320VC5501/5502 DSP External Memory Interface (EMIF) Ref-

erence Guide (literature number SPRU621).

Byte Address

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Figure 3-2. TMS320VC5502 Memory Map

Functional Overview

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