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TMS320VC5502 bảng dữ liệu(PDF) 93 Page - Texas Instruments

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tên linh kiện TMS320VC5502
Giải thích chi tiết về linh kiện  Fixed-Point Digital Signal Processor
PDF  189 Pages
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TMS320VC5502 bảng dữ liệu(HTML) 93 Page - Texas Instruments

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TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
3.12.2.5
Parallel GPIO Direction Register 1 (PGPIODIR1)
15
14
13
12
11
10
9
8
IO31DIR
IO30DIR
IO29DIR
IO28DIR
IO27DIR
IO26DIR
IO25DIR
IO24DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
IO23DIR
IO22DIR
IO21DIR
IO20DIR
IO19DIR
IO18DIR
IO17DIR
IO16DIR
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value at reset
Figure 3-38. Parallel GPIO Direction Register 1 Layout (0x4404)
Table 3-41. Parallel GPIO Direction Register 1 Bit Field Description
(1)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
IOxDIR
15-0
R/W
0000000000000000
Data direction bits that configure corresponding I/O pins either as
inputs or outputs. See Table 3-36, TMS320VC5502 PGPIO
Cross-Reference.
•
IOxDIR = 0: Configure corresponding pin as an input.
•
IOxDIR = 1: Configure corresponding pin as an output.
(1)
x = value from 16 to 31
3.12.2.6
Parallel GPIO Data Register 1 (PGPIODAT1)
15
14
13
12
11
10
9
8
IO31DAT
IO30DAT
IO29DAT
IO28DAT
IO27DAT
IO26DAT
IO25DAT
IO24DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
7
6
5
4
3
2
1
0
IO23DAT
IO22DAT
IO21DAT
IO20DAT
IO19DAT
IO18DAT
IO17DAT
IO16DAT
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
R/W, pin
LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.
Figure 3-39. Parallel GPIO Data Register 1 Layout (0x4405)
Table 3-42. Parallel GPIO Data Register 1 Bit Field Description
(1)
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
IOxDAT
15-0
R/W
Depends on the signal level on
Data bits used to control the level of the corresponding I/O
the corresponding I/O pin
pins configured as output pins and to monitor the level of
the corresponding I/O pins configured as input pins. See
Table 3-36, TMS320VC5502 PGPIO Cross-Reference.
If IOxDIR = 0, then:
•
IOxDAT = 0: Corresponding I/O pin is read as a low
•
IOxDAT = 1: Corresponding I/O pin is read as a high
If IOxDIR = 1, then:
•
IOxDAT = 0: Set corresponding I/O pin to low
•
IOxDAT = 1: Set corresponding I/O pin to high
(1)
x = value from 16 to 31
Functional Overview
93



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