TMS320VC5502 datasheet(42/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-7. External Bus Selection Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-4

000000000000

Reserved

R/W

Reserved. This reserved bit must be kept as zero during any writes

to XBSR.

Serial Port 2 Mux

R/W

GPIO7

Serial Port 2 Mux Mode bit. Determines the mode of the third serial

Mode

port.

•

Serial Port 2 Mux Mode = 0:

The Serial Port 2 Mux is configured to support the UART and

GPIO. In this mode, the UART is enabled and its two signals

are routed to the corresponding pins on the Serial Port 2 Mux.

GPIO3 and GPIO5 are also routed to their corresponding pins

on the Serial Port 2 Mux.

•

Serial Port 2 Mux Mode = 1:

The Serial Port 2 Mux is configured to support the McBSP2. In

this mode, the McBSP2 is enabled and its six signals are routed

to their corresponding pins on the Serial Port 2 Mux.

Reserved

Parallel/Host Port

R/W

GPIO6

Parallel/Host Port Mux Mode bit. Determines the mode of the

Mux Mode

Parallel Port Mux and the Host Port Mux.

•

Parallel/Host Port Mux Mode = 0:

The Parallel Port Mux is configured to support the HPI in 16-bit

(non-multiplexed) mode and PGPIO. In this mode, the HPI is

enabled and its 16 address, 16 data, and 9 control signals are

routed to their corresponding pins on the Parallel Port Mux. The

rest of the pins are routed to PGPIO. The EMIF cannot be used

in this mode.

The Host Port Mux is configured to support PGPIO. In this

mode, the Host Port Mux pins will be routed to PGPIO.

•

Parallel/Host Port Mux Mode = 1:

The Parallel Port Mux is configured to support the 32-bit EMIF.

In this mode, the EMIF is enabled and its 20 address, 32 data,

and 16 control signals are routed to their corresponding pins on

the Parallel Port Mux.

The Host Port Mux is configured to support the HPI in 8-bit

(multiplexed) mode. In this mode, the HPI is enabled and its

eight data/address and two control signals are routed to their

corresponding pins on the Host Port Mux.

Functional Overview

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