TMS320VC5502 datasheet(62/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-13. PLL Control/Status Register Bit Field Description (continued)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

PLLEN

R/W

PLL mode enable. This bit controls the multiplexer before dividers

D1, D2, and D3.

•

PLLEN = 0:

Bypass mode. Divider D1 and PLL are bypassed. SYSCLK1 to 3

divided down directly from input reference clock.

•

PLLEN = 1:

PLL mode. Divider D1 and PLL are not bypassed. SYSCLK1

to 3 divided down from PLL output.

3.10.5.2

PLL Multiplier Control Register (PLLM)

Reserved

R, 00000000

Reserved

PLLM

R, 000

R/W, 00000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-16. PLL Multiplier Control Register Layout (0x1C88)

Table 3-14. PLL Multiplier Control Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15:5

00000000000

Reserved. Reads return 0. Writes have no effect.

PLLM

4:0

R/W

00000

PLL multiplier-select

•

PLLM = 00000-00001: Reserved

•

PLLM = 00010: Times 2

•

PLLM = 00011: Times 3

•

PLLM = 00100: Times 4

•

PLLM = 00101: Times 5

•

PLLM = 00110: Times 6

•

PLLM = 00111: Times 7

•

PLLM = 01000: Times 8

•

PLLM = 01001: Times 9

•

PLLM = 01010: Times 10

•

PLLM = 01011: Times 11

•

PLLM = 01100: Times 12

•

PLLM = 01101: Times 13

•

PLLM = 01110: Times 14

•

PLLM = 01111: Times 15

•

PLLM = 10000–11111: Reserved

Functional Overview

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