TMS320VC5502 datasheet(60/189 Pages) TI

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3.10.5

PLL Control Registers

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.10.4.2

Fast Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Fast Peripherals Clock

Group. The PLLDIV1 value of the PLL Divider1 Register (PLLDIV1) should not be set in a manner that

makes the frequency for this clock group greater than 150 MHz. There must be no activity in the modules

included in the Fast Peripherals Clock Group when the value of PLLDIV1 is being changed. It is

recommended that the fast peripheral modules be put in IDLE mode before changing the PLLDIV1 value.

3.10.4.3

Slow Peripherals Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the Slow Peripherals Clock

Group. The PLLDIV2 value of the PLL Divider2 Register (PLLDIV2) should not be set in a manner that

makes the frequency for this clock group greater than 150 MHz or greater than the frequency of the Fast

Peripherals Clock Group. There must be no activity in the modules included in the Slow Peripherals Clock

Group when the value of PLLDIV2 is being changed. It is recommended that the slow peripheral modules

be put in IDLE mode before changing the PLLDIV2 value.

3.10.4.4

External Memory Interface Clock Group

Changes to the clock of the C55x Subsystem Clock Group affect the clock of the External Memory

Interface Clock Group. The PLLDIV3 value of the PLL Divider3 Register (PLLDIV3) should not be set in a

manner that makes the frequency for this clock group greater than 100 MHz or greater than the frequency

of the Fast Peripherals Clock Group, whichever is smaller. If an external clock is used, the clock on the

ECLKIN pin can be up to 100 MHz and the output of divider 3 can be set equal to or lower than the

frequency of the Fast Peripherals Clock Group. There must be no external memory accesses when the

value of PLLDIV3 is being changed, this means that the value of PLLDIV3 cannot be changed by a

program that is being executed from external memory. It is recommended that the EMIF be put in IDLE

mode before changing the PLLDIV3 value.

The 5502 PLL control registers are accessible via the I/O memory map.

Table 3-12. PLL Control Registers

ADDRESS

1C80h

PLLCSR

1C82h

CK3SEL

1C88h

PLLM

1C8Ah

PLLDIV0

1C8Ch

PLLDIV1

1C8Eh

PLLDIV2

1C90h

PLLDIV3

1C92h

OSCDIV1

1C98h

WKEN

8400h

CLKOUTSR

8C00h

CLKMD

Functional Overview

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