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3.10.3

EMIF Input Clock Selection

3.10.4

Changing the Clock Group Frequencies

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.10.2.4

External Memory Interface Clock Group

The External Memory Interface Clock Group includes the External Memory Interface (EMIF) module and

the external data bridge modules. The input clock to this clock group is taken from the output of divider 3

(D3). By default, the divider is set to divide its input clock by four, but the divide value can be changed to

divide-by-1 or divide-by-2 by modifying the PLLDIV3 bits of the PLL Divider3 Register (PLLDIV3) through

software. The clock frequency of the External Memory Interface Clock Group must be equal to or less than

that of the Fast Peripherals Clock Group.

The EMIF may be clocked from an external asynchronous clock source through the ECLKIN pin if a

specific EMIF frequency is needed. The source for the EMIF clock can be specified through the

EMIFCLKS pin. If EMIFCLKS is low, then the EMIF will be clocked via the same internal clock that feeds

the data bridge module and performance will be optimal. If EMIFCLKS is high, then an external

asynchronous clock, which can be taken up to 100 MHz, will clock the EMIF. The data throughput

performance may be degraded due to synchronization issues when an external clock source is used for

the EMIF.

DSP software can be used to change the clock frequency of each clock group by setting adequate values

in the PLL control registers. Figure 3-14 shows which PLL control registers affect the different portions of

the clock generator. The following sections describe the procedures for changing the frequencies of each

clock group.

Functional Overview

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