TMS320VC5502 datasheet(26/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 2-4. Signal Descriptions (continued)

MULTIPLEXED

OTHER(2)

FUNCTION

NAME

SIGNAL NAME

TYPE(1)

The C12 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO32 or external memory interface

control signal EMIF.SDCKE. The function of the C12 pin is determined by the state

C12

I/O/Z

of the GPIO6 pin during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during

reset. The C12 pin is set to EMIF.SDCKE if GPIO6 is high during reset. The function

of the C12 pin will be set once the device is taken out of reset (RESET pin

C, D, E, F,

transitions from a low to high state).

G, H, M

Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during

PGPIO32

I/O/Z

reset. The PGPIO32 signal is configured as an input after reset.

EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during

EMIF.SDCKE

O/Z

reset. The EMIF.SDCKE signal is in a high-impedance state during reset and is set

to output after reset with an output value of 1.

The C13 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO33 or external memory interface

control signal EMIF.SOE3. The function of the C13 pin is determined by the state of

C13

I/O/Z

the GPIO6 pin during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during

reset. The C13 pin is set to EMIF.SOE3 if GPIO6 is high during reset. The function

of the C13 pin will be set once the device is taken out of reset (RESET pin

C, D, E, F, transitions from a low to high state).

G, H, M

Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during

PGPIO33

I/O/Z

reset. The PGPIO33 signal is configured as an input after reset.

EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when

GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state

EMIF.SOE3

O/Z

during reset and is set to output after reset with an output value of 1.

The EMIF.SOE3 is intended for glueless FIFO interface.

The C14 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO34 or external memory interface

control signal EMIF.HOLD. The function of the C14 pin is determined by the state of

C14

I/O/Z

the GPIO6 pin during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during

reset. The C14 pin is set to EMIF.HOLD if GPIO6 is high during reset. The function

of the C14 pin will be set once the device is taken out of reset (RESET pin

F, G, H, J,

transitions from a low to high state).

Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during

PGPIO34

I/O/Z

reset. The PGPIO34 signal is configured as an input after reset.

EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset.

EMIF.HOLD

EMIF.HOLD is asserted by an external host to request control of the address, data,

and control signals.

The C15 pin of the Parallel Port serves one of two functions: parallel gen-

eral-purpose input/output (PGPIO) signal PGPIO35 or external memory interface

control signal EMIF.HOLDA. The function of the C15 pin is determined by the state

C15

I/O/Z

of the GPIO6 pin during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during

reset. The C15 pin is set to EMIF.HOLDA if GPIO6 is high during reset. The function

of the C15 pin will be set once the device is taken out of reset (RESET pin

transitions from a low to high state).

C, D, F, G,

Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during

PGPIO35

I/O/Z

H, M

reset. The PGPIO35 signal is configured as an input after reset.

EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during

reset. The EMIF.HOLDA signal is in a high-impedance state during reset and is set

to output after reset with an output value of '1'.

EMIF.HOLDA

O/Z

EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state

and that the EMIF address, data, and control signals are in a high-impedance state,

allowing the external memory interface to be accessed by other devices.

EMIF — Clock Pins

External EMIF input clock. ECLKIN is selected as the input clock to the EMIF

ECLKIN

C, L

when EMIFCLKS is high.

Introduction

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