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TMS320VC5502 bảng dữ liệu(PDF) 85 Page - Texas Instruments |
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TMS320VC5502 bảng dữ liệu(HTML) 85 Page - Texas Instruments |
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85 / 189 page ![]() www.ti.com TMS320VC5502 Fixed-Point Digital Signal Processor SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004 3.11.7.4 Peripheral IDLE Status Register (PISTR) 15 14 13 12 11 10 9 8 Reserved MISC EMIF BIOST WDT PIO URT R, 00 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 7 6 5 4 3 2 1 0 I2C ID IO SP2 SP1 SP0 TIM1 TIM0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 R, 0 LEGEND: R = Read, W = Write, n = value at reset Figure 3-29. Peripheral IDLE Status Register Layout (0x9401) Table 3-31. Peripheral IDLE Status Register Bit Field Description BIT NAME BIT NO. ACCESS RESET VALUE DESCRIPTION Reserved 15-14 R 00 Reserved MISC 13 R 0 MISC bit • MISC = 0: Miscellaneous modules are active • MISC = 1: Miscellaneous modules are disabled Miscellaneous modules include the XBSR, TIMEOUT Error Register, XBCR, Timer Signal Selection Register, CLKOUT Select Register, and Clock Mode Control Register. EMIF 12 R 0 EMIF bit • EMIF = 0: EMIF module is active • EMIF = 1: EMIF module is disabled BIOST 11 R 0 BIOS timer bit • BIOST = 0: DSP/BIOS timer is active • BIOST = 1: DSP/BIOS timer is disabled WDT 10 R 0 Watchdog timer bit • WDT = 0: WDT is active • WDT = 1: WDT is disabled PIO 9 R 0 Parallel GPIO bit • PIO = 0: Parallel GPIO is active • PIO = 1: Parallel GPIO is disabled URT 8 R 0 UART bit • URT = 0: UART is active • URT = 1: UART is disabled I2C 7 R 0 I2C bit • I2C = 0: I2C is active • I2C = 1: I2C is disabled ID 6 R 0 ID bit • ID = 0: ID is active • ID = 1: ID is disabled IO 5 R 0 IO bit • IO = 0: GPIO is active • IO = 1: GPIO is disabled SP2 4 R 0 McBSP2 bit • SP2 = 0: McBSP2 is active • SP2 = 1: McBSP2 is disabled SP1 3 R 0 McBSP1 bit • SP1 = 0: McBSP1 is active • SP1 = 1: McBSP1 is disabled Functional Overview 85 |
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