TMS320VC5502 datasheet(80/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 3-28. IDLE Configuration Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-10

000000

Reserved

CLKEI

R/W

Extended device clock generator idle control bit. The CLKEI bit must be

set to 1 along with the CLKI bit in order to properly place the device clock

generator in idle.

•

CLKI = 0 and CLKEI = 0:

Device clock generator module remains active after execution of an

IDLE instruction.

•

CLKI = 1 and CLKEI = 1:

Device clock generator is disabled after execution of an IDLE

instruction.

Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1

and executing the IDLE instruction will generate a bus error interrupt if

CLKEI is not set to 1.

Disabling the clock generator provides the lowest level of power reduction

by stopping the system clock. Whenever the clock generator is idled, the

CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits

must be set to 1 in order to ensure a proper power-down mode. A bus

error interrupt will be generated if the idle instruction is executed when

CLKI = 1 and any of these bits are not set to 1.

IPORTI

R/W

IPORT idle control bit. The IPORT is used for all ICACHE transactions.

•

IPORTI = 0:

IPORT remains active after execution of an IDLE instruction

•

IPORTI = 1:

IPORT is disabled after execution of an IDLE instruction

MPORTI

R/W

MPORT idle control bit. The MPORT is used for all DMA and HPI

transactions.

•

MPORTI = 0:

MPORT remains active after execution of an IDLE instruction

•

MPORTI = 1:

MPORT is disabled after execution of an IDLE instruction

XPORTI

R/W

XPORT idle control bit. The XPORT is used for all I/O memory

transactions.

•

XPORTI = 0:

XPORT remains active after execution of an IDLE instruction

•

XPORTI = 1:

XPORT is disabled after execution of an IDLE instruction

EMIFI

R/W

External Memory Interface (EMIF) idle control bit

•

EMIFI = 0:

EMIF module remains active after execution of an IDLE instruction

•

EMIFI = 1:

EMIF module is disabled after execution of an IDLE instruction

CLKI

R/W

Device clock generator idle control bit. The CLKEI bit must be set to 1

along with the CLKI bit in order to properly place the device clock

generator in idle.

•

CLKI = 0 and CLKEI = 0:

Device clock generator module remains active after execution of an

IDLE instruction.

•

CLKI = 1 and CLKEI = 1:

Device clock generator is disabled after execution of an IDLE

instruction.

Any other combination of CLKI and CLKEI is not valid. Setting CLKI to 1

and executing the IDLE instruction will generate a bus error interrupt if

CLKEI is not set to 1.

Disabling the clock generator provides the lowest level of power reduction

by stopping the system clock. Whenever the clock generator is idled, the

CLKEI, CPUI, MPI, ICACHEI, EMIFI, XPORTI, MPORTI, and IPORTI bits

must be set to 1 in order to ensure a proper power-down mode. A bus

error interrupt will be generated if the idle instruction is executed when

CLKI = 1 and any of these bits are not set to 1.

Functional Overview

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