TMS320VC5502 datasheet(57/189 Pages) TI

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3.10.2

Clock Groups

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.10.1.4

Frequency Ranges for Internal Clocks

There are specific minimum and maximum reference clocks for all of the internal clocks. Table 3-11 lists

the minimum and maximum frequencies for the internal clocks of the TMS320VC5502.

Table 3-11. Internal Clocks Frequency Ranges

(1)

VC5502-200

VC5502-300

CLOCK SIGNAL

UNIT

MIN

MAX

MIN

MAX

OSCOUT (CLKMD = 0)

MHz

PLLREF (PLLEN = 1)

100

MHz

PLLOUT (PLLEN = 1)

200

300

MHz

CLKOUT3

–

200

–

300

MHz

SYSCLK1

–

150

–

150

MHz

SYSCLK2

–

SYSCLK1

–

SYSCLK1

MHz

SYSCLK3

–

SYSCLK1(2)

–

SYSCLK1(2)

MHz

(1)

Also see the electrical specification (timing requirements and switching characteristics parameters) in Section 5.6, Clock Options, of this

data manual.

(2)

When an internal clock is used for the EMIF module, the frequency for SYSCLK3 must also be less than or equal to 100 MHz. When an

external clock is used, the maximum frequency of SYSCLK3 can be equal to or less than the frequency of SYSCLK1; however, the

frequency of the clock signal applied to the ECLKIN pin must be less than or equal to 100 MHz.

The TMS320VC5502 has four clock groups: the C55x Subsystem Clock Group, the Fast Peripherals Clock

Group, the Slow Peripherals Clock Group, and the External Memory Interface Clock Group. Clock groups

allow for lower power and performance optimization since the frequency of groups with no high-speed

requirements can be set to 1/4 or 1/2 the frequency of other groups.

3.10.2.1

C55x Subsystem Clock Group

The C55x Subsystem Clock Group includes the C55x CPU core, internal memory (DARAM and ROM), the

ICACHE, and all CPU-related modules. The input clock to this clock group is taken from the CLKOUT3

signal (as shown in Figure 3-12), the source of which can be controlled through the CLKOUT3 Select

recommended that the CK3SEL bits of the CK3SEL register be kept at their default value of '1011b' during

normal operation. When operating the clock generator in PLL Mode, the frequency of CLKOUT3 can be

set by adjusting the divider and multiplier values of D0 and M1 through the PLLDIV0 and PLLM registers,

respectively.

3.10.2.2

Fast Peripherals Clock Group

The Fast Peripherals Clock Group includes the DMA, HPI, and the timers. The input clock to this clock

group is taken from the output of divider 1 (D1) (as shown in Figure 3-12). By default, the divider is set to

divide its input clock by four, but the divide value can be changed to divide-by-1 or divide-by-2 by

modifying the PLLDIV1 bits of the PLL Divider1 Register (PLLDIV1) through software.

3.10.2.3

Slow Peripherals Clock Group

The Slow Peripherals Clock Group includes the McBSPs, I

2C, and the UART. The input clock to this clock

group is taken from the output of divider 2 (D2). by default, the divider is set to divide its input clock by

four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of

the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock

Group must be equal to or less than that of the Fast Peripherals Clock Group.

Functional Overview

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