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3.5.1

Timer Interrupts

Others

IWCON

RESET

INT3

NMI

TINT1

TINT0

TINT

RESET

INT3

NMI/WDTOUT

Timer0

TINT

Timer1

TINT

Watchdog

Timer

TMS320VC5502 DSP

Interrupt Logic

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT, respectively.

Timer 0, Timer 1, and the Watchdog Timer are each assigned a pin: TIM0 pin is assigned to Timer 0,

TIM1 is assigned to Timer 1, and NMI/WDTOUT is used by the Watchdog Timer. The input (TIN) or output

(TOUT) signal of Timer 0, Timer 1, and the Watchdog Timer can be connected to their respective pins via

the Timer Signal Selection Register (TSSR).

The DSP/BIOS timer input, output, and interrupt signals are not internally connected. No interrupts are

needed from this timer; therefore, the timer interrupt signal is not internally connected to the CPU interrupt

logic.

The interrupt signal (TINT) of the Watchdog Timer can be internally connected to the NMI, RESET, and

INT3 signals via the TSSR.

Note that the NMI/WDTOUT pin has a dual function: Watchdog Timer pin and NMI input pin. The function

of the NMI/WDTOUT pin can be selected through the TSSR.

For more information on the 5502 timers, see the TMS320VC5501/5502 DSP Timers Reference Guide

(literature number SPRU618).

As stated earlier, each timer has one input, one output, and one interrupt signal: TIN, TOUT, and TINT,

respectively. The interrupt signals of Timer 0 and Timer 1 are directly connected to the interrupt logic of

the DSP (see Figure 3-6). The interrupts for Timer 0 and Timer 1 are maskable and can be enabled or

disabled through the TINT0 and TINT1 bits of the interrupt enable registers (IER0 and IER1); setting

TINT0 of IER0 to '1' enables the interrupt for Timer 0 and setting TINT1 of IER1 enables the interrupt for

Timer 1.

Figure 3-6. Timer Interrupts

Functional Overview

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