TMS320VC5502 datasheet(100/189 Pages) TI

100 / 189 page

www.ti.com

3.14.2

DPORT Interface

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.14.1.2

XPORT Bus Error Register (XERR)

The XPORT Bus Error Register bit layout is shown in Figure 3-45 and the bits are described in

Table 3-50.

INTERR

Reserved

PERITO

Reserved

R, 0

R, 00

R, 0

R, 0000

Reserved

EBUS

DBUS

Reserved

R, 000

R, 0

R, 000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-45. XPORT Bus Error Register Layout (0x0102)

Table 3-50. XPORT Bus Error Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

INTERR

INTERR bit

•

INTERR = 0: No error

•

INTERR = 1: An error occurred during an access to one of the

registers listed in Table 3-48.

Reserved

14–13

Reserved

PERITO

PERITO bit

•

PERITO = 0: No error

•

PERITO = 1: A time-out error occurred during an access to a

peripheral register.

Reserved

11–5

0000000

Reserved

EBUS

EBUS error bit(1)

•

EBUS = 0: No error

•

EBUS = 1: An error occurred during an EBUS access (write) to

one of the registers listed in Table 3-48.

DBUS

DBUS error bit(1)

•

DBUS = 0: No error

•

DBUS = 1: An error occurred during a DBUS access (read) to

one of the registers listed in Table 3-48.

Reserved

2–0

000

Reserved

(1)

See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.

The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on

the EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write

posting registers, which are freely associated with E and F bus writes, exist within the DPORT and are

used to store the write address and data so that writes can be zero wait state for the CPU. External

memory writes will not generate stalls to the CPU unless the two write posting registers are filled. Write

posting is enabled by setting the WPE bit of the DCR to 1.

The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external

memory has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit

of the Time-Out Control Register (TOCR). This function is not recommended during normal operation of

the 5502.

100

Functional Overview

TMS320VC5502 bảng dữ liệu(PDF) 100 Page - Texas Instruments

TMS320VC5502 bảng dữ liệu(HTML) 100 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL