TMS320VC5502 datasheet(101/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

The DPORT can be placed into idle through the EMIFI bit of the Idle Control Register (ICR) and executing

the IDLE instruction. When the DPORT is in idle, it will stop accepting new EMIF requests. If there is a

request from the CPU or the EMIF, the DPORT will not respond and hang. The ICR register will generate

a bus error if the DPORT is idled without the CPU or Master Port domains being in idle.

3.14.2.1

DPORT Configuration Register (DCR)

The DPORT Configuration Register bit layout is shown in Figure 3-46 and the bits are described in

Table 3-51.

Reserved

R, 00000000

WPE

Reserved

R/W, 0

R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-46. DPORT Configuration Register Layout (0x0200)

Table 3-51. DPORT Configuration Register Bit Field Description

(1)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-8

00000000

Reserved

WPE

R/W

Write Posting Enable bit(1)

•

WPE = 0: Write posting disabled

•

WPE = 1: Write posting enabled

Reserved

6-0

0000000

Reserved

(1)

Write posting should not be enabled or disabled while the EMIF is conducting a transaction with external memory.

3.14.2.2

DPORT Bus Error Register (DERR)

The DPORT Bus Error Register bit layout is shown in Figure 3-47 and the bits are described in

Table 3-52.

Reserved

EMIFTO

Reserved

R, 000

R, 0

R, 0000

Reserved

R, 0000000

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-47. DPORT Bus Error Register Layout (0x0202)

Functional Overview

101

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