TMS320VC5502 datasheet(15/189 Pages) TI

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TMS320VC5502

1.1 Features

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

• Programmable Low-Power Control of Six

• High-Performance, Low-Power, Fixed-Point

Device Functional Domains

TMS320C55x™ Digital Signal Processor (DSP)

–

3.33-/5-ns Instruction Cycle Time

• On-Chip Peripherals

–

300-/200-MHz Clock Rate

–

Six-Channel Direct Memory Access (DMA)

Controller

–

16K-Byte Instruction Cache (I-Cache)

–

Three Multichannel Buffered Serial Ports

–

One/Two Instructions Executed per Cycle

(McBSPs)

–

Dual Multipliers [Up to 600 Million

–

Programmable Analog Phase-Locked Loop

Multiply-Accumulates Per Second

(APLL) Clock Generator

(MMACS)]

–

General-Purpose I/O (GPIO) Pins and a

–

Two Arithmetic/Logic Units (ALUs)

Dedicated Output Pin (XF)

–

One Program Bus, Three Internal

–

8-Bit/16-Bit Parallel Host-Port Interface

Data/Operand Read Buses, and Two

(HPI)

Internal Data/Operand Write Buses

–

Four Timers

• Instruction Cache (16K Bytes)

• Two 64-Bit General-Purpose Timers

• 32K x 16-Bit On-Chip RAM That is Composed

• 64-Bit Programmable Watchdog Timer

of Eight Blocks of 4K

× 16-Bit Dual-Access

• 64-Bit DSP/BIOS™ Counter

RAM (DARAM) (64K Bytes)

–

Inter-Integrated Circuit (I

2C) Interface

• 16K × 16-Bit One-Wait-State On-Chip ROM

–

Universal Asynchronous Receiver/

(32K Bytes)

Transmitter (UART)

• 8M × 16-Bit Maximum Addressable External

• On-Chip Scan-Based Emulation Logic

Memory Space

• IEEE Std 1149.1(1) (JTAG) Boundary Scan

• 32-Bit External Parallel Bus Memory Support-

Logic

ing External Memory Interface (EMIF) With

• Packages:

General-Purpose Input/Output (GPIO) Capabili-

–

176-Terminal LQFP (Low-Profile Quad

ties and Glueless Interface to:

Flatpack) (PGF Suffix)

–

Asynchronous Static RAM (SRAM)

–

201-Terminal MicroStar BGA™ (Ball Grid

–

Asynchronous EPROM

Array) (GZZ and ZZZ Suffixes)

–

Synchronous DRAM (SDRAM)

• 3.3-V I/O Supply Voltage

–

Synchronous Burst RAM (SBRAM)

• 1.26-V Core Supply Voltage

• Emulation/Debug Trace Capability Saves Last

16 Program Counter (PC) Discontinuities and

Last 32 PC Values

(1)

IEEE Standard 1149.1 - 1990 Standard Test Access Port and

Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320,

TMS320C5000 are trademarks of Texas Instruments.

I2C bus is a trademark of Koninklijke Philips Electronics N.V.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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