TMS320VC5502 datasheet(75/189 Pages) TI

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3.11.3

Module Behavior at Entering IDLE State

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3. Set the WKEN register to specify which event will wake up internal oscillator [e.g., set bit 1 to have

interrupt 0 (INT0) wake up the oscillator]. (1)

4. Write a '1' to all peripheral module bits in the PICR (write 0x3FFF to PICR).

5. Write a '1' to the HPI and DMA bits in MICR (write 0x0003 to MICR).

6. Write a '1' to all domain bits and bit 9 in the ICR (write 0x03FF to ICR).

7. Execute the IDLE instruction.

8. Internal oscillator is set to power-down mode, PLL core is set to power-down mode, and all internal

clocks are disabled.

Note that the internal oscillator can be awakened through an NMI or external interrupt as long as that

event is specified in the Oscillator Wakeup Control Register and, in the case of an external interrupt, the

interrupt is enabled in the CPU’s Interrupt Enable Register.

(1)

Maskable external interrupts must be enabled through IER prior to setting the 5502 to IDLE.

All transactions must be completed before entering the IDLE state. Table 3-25 lists the behavior of each

module before entering the IDLE state.

Table 3-25. Peripheral Behavior at Entering IDLE State

MODULE BEHAVIOR AT ENTERING IDLE STATE

CLOCK DOMAIN

MODULES

(ASSUMING THE IDLE CONTROL IS SET)

CPU

Enter IDLE after CPU stops pipeline.

Interrupt Controller

Enter IDLE after CPU stops.

CPU

IDLE Controller

Enter IDLE after CPU stops.

PLL Controller

Enter IDLE after CPU stops.

Enter IDLE state after current DMA transfer to internal memory, EMIF,

or peripheral, or enter IDLE state immediately if no transfer exists.

DMA

DMA has function of Auto-wakeup/Idle with McBSP data transfer during

Master Port

IDLE.

HPI

Enter IDLE state immediately. Software has to take care of HPI activity.

Enter IDLE state after current data transfer from EMIF or program fetch

ICACHE

from CPU finishes, or enter IDLE state immediately if no transfer and

no access exist.

External Bus Selection Register Enter IDLE after CPU stops.

Timer Signal Selection Register Enter IDLE after CPU stops.

CLKOUT Selection Register

Enter IDLE after CPU stops.

External Bus Control Register

Enter IDLE after CPU stops.

Clock Mode Control Register

Enter IDLE after CPU stops.

Timer0/1 and WDT

Enter IDLE state immediately

DSP/BIOS Timer

Enter IDLE state immediately

External Clock and Frame:

Enter IDLE state after current McBSP activity is finished or enter IDLE

Peripheral

state immediately if no activity exists. McBSP has function of

MCBSP0/1/2

Auto-wakeup/Idle with DMA transfer during IDLE.

Internal Clock and Frame:

Enter IDLE state immediately if both transmitter and receiver are in

reset (XRST = 0 and RRST = 0). IDLE state not entered otherwise.

GPIO

Enter IDLE state immediately.

Enter IDLE state after current I2C activity is finished or enter IDLE state

I2C

immediately if no activity exists.

Enter IDLE state after current UART activity is finished or enter IDLE

UART

state immediately if no activity exists.

Parallel GPIO

Enter IDLE state immediately.

Functional Overview

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