TMS320VC5502 datasheet(95/189 Pages) TI

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3.13

External Bus Control Register

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.12.2.9

Parallel GPIO Data Register 2 (PGPIODAT2)

Reserved

IO45DAT

IO44DAT

IO43DAT

IO42DAT

IO41DAT

IO40DAT

R/W, 00

R/W, pin

IO39DAT

IO38DAT

IO37DAT

IO36DAT

IO35DAT

IO34DAT

IO33DAT

IO32DAT

R/W, pin

LEGEND: R = Read, W = Write, n = value at reset, pin = the reset value depends on the signal level on the corresponding I/O pin.

Figure 3-42. Parallel GPIO Data Register 2 Layout (0x4408)

Table 3-45. Parallel GPIO Data Register 2 Bit Field Description

(1)

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15-14

R/W

Reserved

IOxDAT

13-0

R/W

Depends on the signal level on

Data bits used to control the level of the I/O pins

the corresponding I/O pin

configured as output pins, and to monitor the level of the

corresponding I/O pins configured as input pins. See

Table 3-36, TMS320VC5502 PGPIO Cross- Reference.

If IOxDIR = 0, then:

•

IOxDAT = 0: Corresponding I/O pin is read as a low

•

IOxDAT = 1: Corresponding I/O pin is read as a high

If IOxDIR = 1, then:

•

IOxDAT = 0: Set corresponding I/O pin to low

•

IOxDAT = 1: Set corresponding I/O pin to high

(1)

x = value from 32 to 45

The External Bus Control Register is used to disable/enable the bus pullups, pulldowns, and bus holders

of the 5502 pins. Table 3-46 lists which 5502 pins have pullups, pulldowns, and bus holders, and which bit

on the XBCR enables/disables that feature. Please note that for pins with dual functionality (e.g., HC0,

HC1, C0, etc.), the bus holder, pullup, and pulldown feature of each pin can be enabled or disabled

regardless of the function of the pin at the time.

Functional Overview

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