TMS320VC5502 datasheet(61/189 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

3.10.5.1

PLL Control / Status Register (PLLCSR)

Reserved

R, 00000000

Reserved

STABLE

LOCK

Reserved

PLLRST

OSCPWRDN

PLLPWRDN

PLLEN

R, 0

R, 1

R, 0

R/W, 1

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-15. PLL Control/Status Register Layout (0x1C80)

Table 3-13. PLL Control/Status Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

Reserved

15:7

000000000

Reserved. Reads return 0. Writes have no effect.

STABLE

Oscillator output stable. This bit indicates if the OSCOUT output has

stabilized.

•

STABLE = 0:

Oscillator output is not yet stable. Oscillator counter is not done

counting 41,032 reference clock cycles.

•

STABLE = 1:

Oscillator output is stable. This is true if any one of the three

cases is true:

a) Oscillator counter has finished counting.

b) Oscillator counter is disabled.

c) Test mode.

LOCK

Lock mode indicator. This bit indicates whether the clock generator

is in its lock mode.

•

LOCK = 0:

The PLL is in the process of getting a phase lock.

•

LOCK = 1:

The clock generator is in the lock mode. The PLL has a phase

lock and the output clock of the PLL has the frequency

determined by the PLLM register and PLLDIV0 register.

Reserved

Reserved. Reads return 0. Writes have no effect.

PLLRST

R/W

Asserts RESET to PLL

•

PLLRST = 0: PLL reset released

•

PLLRST = 1: PLL reset asserted

OSCPWRDN

R/W

Sets internal oscillator to power-down mode

•

OSCPWRDN = 0:

Oscillator operational

•

OSCPWRDN = 1:

Oscillator set to power-down mode based on state of CLKMD0

bit of Clock Mode Control Register (CLKMD).

–

When CLKMD0 = 0, the internal oscillator is set to

power-down mode when the clock generator is set to its idle

mode [CLKIS bit of the IDLE Status Register (ISTR)

becomes 1].

–

When CLKMD0 = 1, the internal oscillator is set to

power-down mode immediately after the OSCPWRDN bit is

set to 1.

PLLPWRDN

R/W

Selects PLL power down

•

PLLPWRDN = 0: PLL operational

•

PLLPWRDN = 1: PLL placed in power-down state

Functional Overview

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