TMS320VC5502 datasheet(89/189 Pages) TI

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3.12.2

Parallel Port General-Purpose I/O (PGPIO)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Four address pins (A[21:18]), 16 data pins (D[31:16]), 16 control signals (C[15:0]), 8 host data pins

(HD[7:0]), and 2 HPI control pins (HC0, HC1) can be individually enabled as PGPIO when the

Parallel/Host Port Mux Mode bit field of the External Bus Selection Register (XBSR) is cleared for

non-multiplexed HPI mode (see Table 3-36). These pins are controlled by three sets of registers: the

PGPIO enable registers, the PGPIO direction registers, and the PGPIO data registers.

• The PGPIO enable registers PGPIOEN0-PGPIOEN2 (see Figure 3-34, Figure 3-37, and Figure 3-40)

determine if the pin serves as PGPIO or if it is placed in high-impedance state.

• The PGPIO direction registers PGPIODIR0-PGPIODIR2 (see Figure 3-35, Figure 3-38, and Fig-

ure 3-41) determine if the pin is an input or output.

• The PGPIO data registers PGPIODAT0-PGPIODAT2 (see Figure 3-36, Figure 3-39, and Figure 3-42)

store the value read or written externally.

NOTE

The enable registers PGPIOENn cannot override the External Bus Selection Register

(XBSR) setting.

Table 3-36. TMS320VC5502 PGPIO Cross-Reference

PARALLEL/HOST PORT MUX MODE = 0

PARALLEL/HOST PORT MUX MODE = 1

(HPI NON-MULTIPLEX)

(FULL EMIF)

EMIF Address Bus

A[21:18]

PGPIO[3:0]

EMIF.A[21:18]

EMIF Data Bus

D[31:16]

PGPIO[19:4]

EMIF.D[31:16]

EMIF Control Bus

PGPIO20

EMIF.ARE/SADS/SDCAS/SRE

PGPIO21

EMIF.AOE/SOE/SDRAS

PGPIO22

EMIF.AWE/SWE/SDWE

PGPIO23

EMIF.ARDY

PGPIO24

EMIF.CE0

PGPIO25

EMIF.CE1

PGPIO26

EMIF.CE2

PGPIO27

EMIF.CE3

PGPIO28

EMIF.BE0

PGPIO29

EMIF.BE1

C10

PGPIO30

EMIF.BE2

C11

PGPIO31

EMIF.BE3

C12

PGPIO32

EMIF.SDCKE

C13

PGPIO33

EMIF.SOE3

C14

PGPIO34

EMIF.HOLD

C15

PGPIO35

EMIF.HOLDA

HPI Data Bus

HD[7:0]

PGPIO[43:36]

HPI.HD[7:0]

HPI Control Bus

HC0

PGPIO44

HPI.HAS

HC1

PGPIO45

HPI.HBIL

Functional Overview

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