TMS320VC5502 datasheet(132/189 Pages) TI

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5.6.3

Clock Generation in Bypass Mode (APLL Disabled)

CLKOUT

CLKIN

C10

C11

(A ) The relationship of CLKIN to CLKOUT depends on the system clock selected to drive CLKOUT. The waveform relationship

shown in this figure is intended to illustrate the timing parameters only and may differ based on configuration.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-2 and Table 5-3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5-3).

Table 5-2. CLKIN in Bypass Mode Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

MIN

MAX

tc(CI)

Cycle time, CLKIN(1)

APLL Synthesis Disabled

(2)

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

0.4 * tc(CI)

C11

tw(CIH)

Pulse duration, CLKIN high

0.4 * tc(CI)

(1)

If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5-1.

(2)

This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

Table 5-3. CLKOUT in Bypass Mode Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

TYP

MAX

tc(CO)

Cycle time, CLKOUT

K * tc(CI)(1)

(2)

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

K * tc(CI) /2 – 1

K * tc(CI) /2 + 1

tw(COH)

Pulse duration, CLKOUT high

K * tc(CI) /2 – 1

K * tc(CI) /2 + 1

(1)

K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and

SYSCLK1 is set to the CPU clock divided by four, use K = 4.

(2)

This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

Figure 5-3. Bypass Mode Clock Timings

132

Specifications

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