SH33F2801PSLASH032PR datasheet(12/407 Pages) SINOWEALTH

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SH33F2801

7.3

Special-purpose Registers

ARM Star Core also has several special registers on core level, as shown in the following table:

Table7-1

ARM Star Core Special Registers and Their Functions

Function

xPSR

Provide ALU flags (zero flag, carry flag, negative flag, overflow flag), execution status, and current

executing interrupt number

PRIMASK

Disable all interrupts except the non-maskable interrupt(NMI) and Hard Fault

FAULTMASK

Disable all interrupts except the NMI

BASEPRI

Disable all interrupts of specific priority level or lower priority level

CONTROL

Define privilege status and stack pointer selection

7.3.1

Program Status Registers

The program status registers are subdivided into three status registers. These three registers are: application PSR

(APSR), interrupt PSR (IPSR), and execution PSR (EPSR). The three PSRs can be accessed together or separately using the

special register access instructions MSR and MRS. When they are accessed as a collective item, the name xPSR is used.

7.3.1.1

Application PSR

Application PSR (APSR) contains condition code flags. The ARM Star processor stores the condition code flags on the

stack before entering the exception. You can read the APSR using MRS instruction and can change the APSR using the MSR

instruction, but EPSR and IPSR are read-only.

b31

b30

b29

b28

b27

b26

b25

b24

b23

b22

b21

b20

b19

b18

b17

b16

Reserved

b15

b14

b13

b12

b11

b10

Reserved

Bit

Sign

Description

Negative

1: the result is negative

0: the result is positive

Zero

1: the result is 0

0: the result is not 0

Carry/borrow

1: carry or borrow

0: no carry or borrow

Overflow

1: overflow

0: no overflow

DSP Overflow and Sticky saturation flag

26 - 0

Reserved

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