SH33F2801PSLASH032PR datasheet(86/407 Pages) SINOWEALTH

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SH33F2801

13.3.1

Default Configuration of I/O Pins

During reset and after reset, the I/O port function is configured as “GPIO floating input” function, except for the SWJ

interface.

After system reset, SWD interface is selected as the default function. In order to ensure proper entry into the debug mode,

it is necessary to keep the SWD port as non-floating status. To achieve this, the corresponding SWD pins are set as follows

after reset:



SWDIO: input pull-up



SWCLK: input pull-down

Once the SWD interface is released by the user code (see control bit SWDCFG@SYSCFG_SAFR), the software can use

these I/O ports as general purpose I/O ports.

Unlike the SWD interface, the external oscillator interface XTAL1/XTAL2 is GPIO function by default. The XTAL interface

attribute needs to be turned on by the user code (see control bit OSCCFG@SYSCFG_SAFR).

13.3.2

I/O Control Register

Each I/O port has four 32-bit registers for configuring the working modes: MODER, OTYPER, PUPDR and AFR.

MODER: set input and output direction;

OTYPER: set the output type, which are push-pull output and open-drain output (just for individual pins);

PUPDR: set internal weak pull-up. This register can be set during input and output.

AFR: Set the Alternate Function. There are altogether 8 options AF0 ~ AF7, as detailed in the "Alternate Mapping table".

The system interface does not belong to AFR setting.

13.3.3

I/O Data Register

Each GPIO port has two 16-bit data registers: IDR, ODR.

IDR: input data register, read access to the input data register can get I/O status

ODR: output data register, the value written to the output data register (ODR) is output to the corresponding I/O pin..

13.3.4

I/O Bit Set And Bit Reset

Bit set and reset register (BSRR) is a 32-bit register that allows each bit of the Output Register (ODR) to be independently

set and cleared (reset).

The lower 16 bits of the BSRR are set operations, and the higher 16 bits are reset operations, allowing simultaneous set

and reset operations on different I/O ports in a single slot of AHB write operation. If set and reset the same I/ O port at the same

time, the set operation has higher priority.

The reading and writing of BSRR can be word, half-word or byte. The following example shows how to use word access to

simultaneously switch two I/O ports in the same level or opposite level:

；Switch PA.0 and PA.1 simultaneously in the same level

GPIOA_BSRR = 0x00000003

GPIOA_BSRR = 0x00030000

；Switch PA.0 and PA.1 simultaneously in the opposite level

GPIOA_BSRR = 0x00020001

GPIOA_BSRR = 0x00010002

If half-word is used to achieve switching simultaneously in the same level with half-word, the method is as

follows:

#define GPIOA_BitSet_ADDR = 0xXX

; point to the base address of GPIO_BSRR_A (used to set)

#define GPIOA_BitReset_ADDR = 0xXX + 2; point to the high half-word offset address of GPIO_BSRR_A

(used to reset)

*(u16*) GPIOA_BitSet_ADDR = 0x03

*(u16*) GPIOA_BitReset_ADDR = 0x03

The bit operation of BSRR on ODR is a single operation, BSRR control bit will be automatically cleared by hardware, and

the corresponding bit of ODR will be modified simultaneously. Also, BSRR is an ‘atom’ operation, user can execute BSRR

operation and ODR operation successively, and two operations will be effective on I/O port sequentially..

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