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SH33F2801P/032PR bảng dữ liệu(PDF) 39 Page - SINOWEALTH Electronic Ltd

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SH33F2801P/032PR bảng dữ liệu(HTML) 39 Page - SINOWEALTH Electronic Ltd

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SH33F2801
39
8.6.1
Flash Acess Control Register (FLASH_ACR)
Offset Address: 0x0000
Reset Value:
0x0000 0000
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
LOCK[15:0]
WO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Reserved
CRST
DCEN Reserv
ed
PRFTE
N
Reserved
LATENCY[2:0]
-
RW
RW
-
RW
-
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Description
31 ~ 16
LOCK[15:0]
Register lock bits
0x5AA5: Unlock this register
Other: Lock this register
When configuring this register, 0x5AA5 must be input to the unlock bits at
the same time. After the operation is completed, it will be automatically locked.
Reading this LOCK bits will firmly get 0x0000.
15 ~ 12
Reserved
-
11
CRST
Reset buffer block
0: no reset buffer
1: reset buffer (data buffer and instruction butter block are reset at the same
time)
10
DCEN
Data buffer enabling
0: Data buffer block is disable
1: Data buffer block is enable
9
Reserved
-
8
PRFTEN
Prefetch buffer enabling
0: Prefetch buffer block is disable
1: Prefetch buffer block is enable
7 ~ 3
Reserved
-
2 ~ 0
LATENCY[2:0]
SYSCLK (system clock) cycle and flash access time configuration
settings
000: 0 waiting status
001: 1 waiting status
010: 2 waiting status
011: 3 waiting status
100: 4 waiting status
101: 5 waiting status
110: 6 waiting status
111: 7 waiting status



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