SH33F2801PSLASH032PR datasheet(83/407 Pages) SINOWEALTH

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SH33F2801

RBITW

Reverses the byte inner bit order of the written data.

0: Remains unchanged

1: Reverses byte inner bit order (refer to Table 12-1 for detailed conversion)

COMPLW

Does a 1's complement transformation to the written data.

0: Remains unchanged

1: Does a 1's complement transformation

9 ~ 8

MODE[1:0]

CRC mode selection, because of the inverse algorithm is used, the

actual value of the polynomial is bitwise reversed.

00: CRC-32 (0x04C11DB7)

01: CRC-16 (generator polynomial is 0x8005)

10: CRC-CITT (generator polynomial is0x1021)

11: CRC-8 (generator polynomial is0x7)

7 ~ 1

Reserved

RELOAD

Reloads the initial value into the data register

1: Writes 1 to reload. Reload INIT@CRC_INIT into the DR@CRC_DR

0: Writes 0 to remain unchanged, this Bit cannot be read, and it is always 0.

12.4.3

CRC Initial Value Register (CRC_INIT)

Offset Address: 0x0008

Reset Value:

0xFFFF FFFF

b31

b30

b29

b28

b27

b26

b25

b24

b23

b22

b21

b20

b19

b18

b17

b16

INIT[31:0]

b15

b14

b13

b12

b11

b10

INIT[31:0]

Bit

Symbol

Description

31 ~ 0

INIT[31:0]

Stores initial value of CRC. After writing 1 to RELOAD@CRC_CR, this

value is automatically loaded into the DR@CRC_DR register.

MODE=0: 32-bit valid

MODE=1: Lower 16-bit valid

MODE=2: Lower 16-bit valid

MODE=3: Lower 8-bit valid

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