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SH33F2801P/032PR bảng dữ liệu(PDF) 67 Page - SINOWEALTH Electronic Ltd

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SH33F2801
67
10.3.10 RESET Status Register (RCC_RSTSTR)
Offset Address: 0x002C
Reset Value:
0x0000 0004
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
Reserved
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Reserved
Reserv
ed
WWDT
RSTF
IWDTR
STF
SWRS
TF
PORS
TF
LVRST
F
PINRS
TF
-
-
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Bit
Symbol
Description
31 ~ 6
Reserved
-
5
WWDTRSTF
Window watchdog reset flag
Set to ‘1’ by hardware when window watchdog reset occurs. Cleared by
software via writing on WWDTRSTFC bit.
0: No window watchdog reset occurs
1: A window watchdog reset occurs
4
IWDTRSTF
Independent watchdog reset flag
Set to ‘1’ by hardware when independent watchdog reset occurs. Cleared by
software via writing on IWDTRSTFC bit.
0: No independent watchdog reset occurs
1: An independent watchdog reset occurs
3
SWRSTF
Software reset flag
Set to ‘1’ by hardware when software reset occurs. Cleared by software via
writing on SWRSTFC bit.
0: No software reset occurs
1: A software reset occurs
2
PORSTF
POR reset flag
Set to ‘1’ by hardware when POR reset occurs. Cleared by software via writing
on PORSTFC bit.
0: No POR reset occurs
1: A POR reset occurs
1
LVRSTF
LVR reset flag
Set to ‘1’ by hardware when LVR reset occurs. Cleared by software via writing
on LVRSTFC bit.
0: No LVR reset occurs
1: An LVR reset occurs
0
PINRSTF
PIN reset flag
Set to ‘1’ by hardware when NRST pin reset occurs. Cleared by software via
writing on PINRSTFC bit.
0: No NRST pin reset occurs
1: An NRST pin reset occurs



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