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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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SH33F2801P/032PR bảng dữ liệu(PDF) 74 Page - SINOWEALTH Electronic Ltd |
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SH33F2801P/032PR bảng dữ liệu(HTML) 74 Page - SINOWEALTH Electronic Ltd |
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74 / 407 page  SH33F2801 74 The window is the largest when RL=WT=0xFF. When the microcontroller enters debug mode (ARM Star core halted), the WWDT counter can continue to operate or stop according to the status of the DBG_WWDT@ DBGCR configuration bit. See the "Debug Interface" part for details. 11.3 IWDT Register IWDT Module Register List (Base Address: 0x4000 2C00) Address Register Name Description 0x4000 2C00 CR Independent watchdog control register 0x4000 2C04 CLR Independent watchdog feeding register 11.3.1 Independent Watchdog Control Register (IWDT_CR) Offset Address: 0x0000 Reset Value: 0x0000 7FFF b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 LOCK[15:0] WO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 IWDTO N IWDTPR[2:0] IWDTRLR[11:0] RW1t RW RW 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Symbol Description 31 ~ 16 LOCK[15:0] Register lock bit 0x5AA5: Unlocks this register Other: Locks this register When configuring this register, the unlock bit must be input 0x5AA5 at the same time. After the operation is completed, it will be automatically locked. 0x0 will be fixedly read when reading this LOCK. 15 IWDTON Independent watchdog enable, this bit is set to '1' by software, but can only be cleared by hardware after reset. This control bit is effective only when OP_IWDT=0101b. 0: IWDT is disabled 1: IWDT is enabled 14 ~ 12 IWDTPR[2:0] Independent watchdog clock pre-division setting 000: Pre-division factor = 4 001: Pre-division factor=8 010: Pre-division factor=16 011: Pre-division factor=32 (default) 100: Pre-division factor=64 101: Pre-division factor=128 110: Pre-division factor=256 111: Pre-division factor=512 11 ~ 0 IWDTRLR[11:0] Independent watchdog reload register Used to define the reload value of the watchdog counter. Note: The reset value of IWDTRLR[11:0] is 0x0FFF. |
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