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SH33F2801P/032PR bảng dữ liệu(PDF) 65 Page - SINOWEALTH Electronic Ltd

tên linh kiện SH33F2801P/032PR
Giải thích chi tiết về linh kiện  32-bit High Performance Motor Control MCU Based on ARM® Star
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SH33F2801P/032PR bảng dữ liệu(HTML) 65 Page - SINOWEALTH Electronic Ltd

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SH33F2801
65
10.3.9
APB Peripheral Clock Enable Register (RCC_APBENR)
Offset Address: 0x0028
Reset Value:
0x0000 0000
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
Reserved
FIFO
2EN
FIFO
1EN
-
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
FIFO
0EN
Rese
rved
CAN
0EN
ADC
EN
PCA
1EN
PCA
0EN
AMO
CEN
WW
DTE
N
TWI0
EN
SPI0
EN
UAR
T2E
N
UAR
T1E
N
UAR
T0E
N
QEIE
N
TIM8
EN
TIM7
EN
RW
-
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Description
31 ~ 14
Reserved
-
17
FIFO2EN
FIFO2 clock enable
Set to ‘1’ or cleared by software
0: FIFO2 clock is disabled
1: FIFO2 clock is enabled
16
FIFO1EN
FIFO1 clock enable
Set to ‘1’ or cleared by software
0: FIFO1 clock is disabled
1: FIFO1 clock is enabled
15
FIFO0EN
FIFO0 clock enable
Set to ‘1’ or cleared by software
0: FIFO0 clock is disabled
1: FIFO0 clock is enabled
14
Reserved
-
13
CANEN
CAN clock enable
Set to ‘1’ or cleared by software
0: CAN clock is disabled
1: CAN clock is enabled
12
ADCEN
ADC clock enable
Set to ‘1’ or cleared by software
0: ADC clock is disabled
1: ADC clock is enabled
11
PCA1EN
PCA1 clock enable
Set to ‘1’ or cleared by software
0: PCA1 clock is disabled
1: PCA1 clock is enabled
10
PCA0EN
PCA0 clock enable
Set to ‘1’ or cleared by software
0: PCA0 clock is disabled
1: PCA0 clock is enabled



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