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SH33F2801P/032PR bảng dữ liệu(PDF) 62 Page - SINOWEALTH Electronic Ltd

tên linh kiện SH33F2801P/032PR
Giải thích chi tiết về linh kiện  32-bit High Performance Motor Control MCU Based on ARM® Star
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SH33F2801P/032PR bảng dữ liệu(HTML) 62 Page - SINOWEALTH Electronic Ltd

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SH33F2801
62
10.3.7
APB Peripheral Reset Register (RCC_APB0RSTR)
Offset Address: 0x001C
Reset Value:
0x0000 0000
b31
b30
b29
b28
b27
b26
b25
b24
b23
b22
b21
b20
b19
b18
b17
b16
Reserved
FIFO
2RS
T
FIFO
1RS
T
-
RW1s
RW1s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
FIFO
0RS
T
Rese
rved
CAN
0RS
T
ADC
RST
PCA
1RS
T
PCA
0RS
T
AMO
CRS
T
WW
DTR
ST
TWI0
RST
SPI0
RST
UAR
T2R
ST
UAR
T1R
ST
UAR
T0R
ST
QEI
RST
TIM8
RST
TIM7
RST
RW1s
-
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
RW1s
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Symbol
Description
31 ~ 18
Reserved
-
17
FIFO2RST
FIFO2 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: FIFO2 reset
16
FIFO1RST
FIFO1 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: FIFO1 reset
15
FIFO0RST
FIFO0 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: FIFO0 reset
14
Reserved
-
13
CAN0RST
CAN0 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: CAN0 reset
12
ADCRST
ADC reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: ADC reset
11
PCA1RST
PCA1 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: PCA1 reset
10
PCA0RST
PCA0 reset
Set to ‘1’ by software, cleared by hardware
0: No effect
1: PCA0 reset



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