SH33F2801PSLASH032PR datasheet(11/407 Pages) SINOWEALTH

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SH33F2801

Core

7.1

ARM® Star Core

The ARM Star processor is a high-performance 32-bit processor that is designed for the microcontroller

market. The processor offers outstanding performance, fast interrupts handling, and enhanced system debug with

extensive breakpoint and trace capabilities.

SH33F2801 uses the latest r0p1 version of the ARM® Star.

7.2

ARM Star processor has registers R0 to R15.

7.2.1

General Purpose Registers

R0-R12 are all 32-bit general purpose registers for data operation.

Note: Some 16-bit Thumb instructions can only access a subset of these registers (low registers, R0 to R7)

7.2.2

Stack Register

Stack pointer (SP) R13: alias of banked registers, SP_process and SP_main.

The

ARM Star contains stack pointers, R13. They are banked so that only one is visible at a time.

Main stack pointer (MSP): The default stack pointer, used by OS kernel and exception handlers.

Process Stack Pointer (PSP): The process stack pointer is used in process mode.

The lowest two bits of the stack pointer are always 0, which means they are always 4-byte aligned.

After the reset is complete, all code uses the main stack. Exception handler (such as SVC) can change the stack used in

thread mode by changing the EXC_RETURN value which it uses when exiting. All exceptions continue to use the main stack.

Stack pointer R13 is banked register, switching between SP_main and SP_process. Of process stack and main stack, only one

is visible at any time, which is indicated by R13.

Except for using the value of EXC_RETURN when exiting from handler mode, writing on CONTROL[1] using the MSR

instruction can also help switch from main stack to process stack in thread mode.

In the field of ARM programming, any event that interrupts the sequential execution of a program is called an exception.

Except for external interrupts, the execution of programs may be interrupted when an instruction performs an "illegal operation"

or accesses prohibited memory, or fault occurs due to various errors, or a non-maskable interrupt occurs. These conditions

above are collectively referred to as exceptions. Exceptions and interrupts can also be mixed in less strict context. In addition,

the program code can also actively request to enter the exception state (usually used for system calls).

7.2.3

Link Register

R14 is the subroutine link register. When a subroutine is called, the returned address is stored by R14.

Different from other processors’ cores, ARM stores the returned address directly in the register in order to reduce the

number of accesses to memories. All level subroutines can be called without accessing memories (stack memories), which

improves the efficiency of subroutine calls. If the level is more than 1, pushing R14 value of the previous level onto the stack is

required. When programming on ARM, recommend using general-purpose registers to save intermediate results for reducing

memory access.

7.2.4

Program Count Register

The program counter (R15) is the current program address. This register can be written to control the program flow. Bit[0]

is always 0, so instructions are always aligned to word or half-word boundaries.

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