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AD9689-2000EBZ bảng dữ liệu(PDF) 121 Page - Analog Devices

tên linh kiện AD9689-2000EBZ
Giải thích chi tiết về linh kiện  Dual Analog-to-Digital Converter
PDF  134 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD9689-2000EBZ bảng dữ liệu(HTML) 121 Page - Analog Devices

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Data Sheet
AD9689
Rev. A | Page 121 of 134
Addr.
Name
Bit(s) Bit Name
Setting
Description
Reset
Access
0x0574 JESD204B Link
Control 4
[7:4] ILAS delay
0x0
R/W
0000
Transmit ILAS on first LMFC after SYNCINB± is deasserted.
0001
Transmit ILAS on second LMFC after SYNCINB± is deasserted.
0010
Transmit ILAS on third LMFC after SYNCINB± is deasserted.
0011
Transmit ILAS on fourth LMFC after SYNCINB± is deasserted.
0100
Transmit ILAS on fifth LMFC after SYNCINB± is deasserted.
0101
Transmit ILAS on sixth LMFC after SYNCINB± is deasserted.
0110
Transmit ILAS on seventh LMFC after SYNCINB± is deasserted.
0111
Transmit ILAS on eighth LMFC after SYNCINB± is deasserted.
1000
Transmit ILAS on ninth LMFC after SYNCINB± is deasserted.
1001
Transmit ILAS on tenth LMFC after SYNCINB± is deasserted.
1010
Transmit ILAS on eleventh LMFC after SYNCINB± is deasserted.
1011
Transmit ILAS on twelfth LMFC after SYNCINB± is deasserted.
1100
Transmit ILAS on thirteenth LMFC after SYNCINB± is deasserted.
1101
Transmit ILAS on fourteenth LMFC after SYNCINB± is deasserted.
1110
Transmit ILAS on fifteenth LMFC after SYNCINB± is deasserted.
1111
Transmit ILAS on sixteenth LMFC after SYNCINB± is deasserted.
3
Reserved
Reserved.
0x0
R
[2:0] Link layer test mode
0x0
R/W
000
Normal operation (link layer test mode disabled).
001
Continuous sequence of /D21.5/ characters.
010
Reserved.
011
Reserved.
100
Modified RPAT test sequence.
101
JSPAT test sequence.
110
JTSPAT test sequence.
111
Reserved.
0x0578 JESD204B
LMFC offset
[7:5] Reserved
Reserved.
0x0
R
[4:0] LMFC phase offset
value
LMFC phase offset value (in frame clocks). Refer to the Deterministic
Latency section.
0x0
R/W
0x0580 JESD204B DID
configuration
[7:0] JESD204B Tx DID
value
JESD204B serial device identification (DID) number.
0x0
R/W
0x0581 JESD204B BID
configuration
[7:4] Reserved
Reserved.
0x0
R
[3:0] JESD204B Tx BID
value
JESD204B serial bank identification (BID) number (extension to DID).
0x0
R/W
0x0583 JESD204B LID0
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 0 LID value
JESD204B serial lane identification (LID) number for Lane 0.
0x0
R/W
0x0584 JESD204B LID1
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 1 LID value
JESD204B serial LID number for Lane 1.
0x1
R/W
0x0585 JESD204B LID2
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 2 LID value
JESD204B serial LID number for Lane 2.
0x2
R/W
0x0586 JESD204B LID3
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 3 LID value
JESD204B serial LID number for Lane 3.
0x3
R/W
0x0587 JESD204B LID4
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 4 LID value
JESD204B serial LID number for Lane 4.
0x4
R/W
0x0588 JESD204B LID5
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 5 LID value
JESD204B serial LID number for Lane 5.
0x5
R/W
0x0589 JESD204B LID6
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 6 LID value
JESD204B serial LID number for Lane 6.
0x6
R/W
0x058A JESD204B LID7
configuration
[7:5] Reserved
Reserved.
0x0
R
[4:0] Lane 7 LID value
JESD204B serial LID number for Lane 7.
0x7
R/W



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