AD9689-2000EBZ datasheet(119/134 Pages) AD

119 / 134 page

Data Sheet

AD9689

Rev. A | Page 119 of 134

Addr.

Name

Bit(s) Bit Name

Setting

Description

Reset

Access

0x0563 Out overrange

status

[7:0] Data format

overrange

Overrange sticky bit status (one bit for each virtual converter). Writing

a 1 to the overrange clear bit clears the corresponding overrange

sticky bit.

0x0

No overrange has occurred.

Overrange has occurred.

0x0564 Out channel

select

[7:1] Reserved

Reserved.

0x0

Converter channel

swap control

0x0

R/W

Normal channel ordering.

Channel swap enabled.

0x056E PLL control

[7:4] JESD204B lane rate

control

0x3

R/W

0000

Lane rate = 6.75 Gbps to 13.5 Gbps.

0001

Lane rate = 3.375 Gbps to 6.75 Gbps.

0011

Lane rate = 13.5 Gbps to 16 Gbps.

0101

Lane rate = 1.6875 Gbps to 3.375 Gbps.

[3:0] Reserved

Reserved.

0x0

0x056F PLL status

PLL lock status

0x0

Not locked.

Locked.

[6:4] Reserved

Reserved.

0x0

PLL loss of lock

Loss of lock sticky bit.

Indicate a loss of lock has occurred at some time. Cleared by setting

[2:0] Reserved

Reserved.

0x0570 fS × 4

configuration

[7:0]

See the fS × 4 Mode section.

0xFF

R/W

0xFE

fS × 4 mode enabled. L = 8; M = 2; F = 2; S = 4; N' = 16; N = 16;

CS = 0; CF = 0; HD = 0.

0xFF

fS × 4 mode disabled. L, M, and F set by Register 0x058B, Bits[4:0];

0x0571 JESD204B Link

Control 1

Standby mode

0x0

R/W

Standby mode forces zeros for all converter samples.

Standby mode forces code group synchronization (/K28.5/ characters).

Tail bit(t) PN

0x0

R/W

Disable.

Enable.

Long transport layer

test

0x0

R/W

JESD204B test samples disabled.

JESD204B test samples enabled; long transport layer test sample

sequence (as specified in JESD204B Section 5.1.6.3) sent on all link lanes.

Lane synchronization

0x1

R/W

Disable FACI uses /K28.7/.

Enable FACI uses /K28.3/ and /K28.7/.

[3:2] ILAS sequence mode

0x1

R/W

Initial lane alignment sequence disabled (JESD204B Section 5.3.3.5).

Initial lane alignment sequence enabled (JESD204B Section 5.3.3.5).

Initial lane alignment sequence always in test mode. JESD204B data

link layer test mode where repeated lane alignment sequence (as

specified in JESD204B Section 5.3.3.8.2) sent on all lanes.

FACI

0x0

R/W

Frame alignment character insertion enabled

(JESD204B Section 5.3.3.4).

Frame alignment character insertion disabled. For debug only

(JESD204B Section 5.3.3.4).

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