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5.14.3

TIM0/TIM1/WDTOUT Interrupt Timings

CLKOUT

TIM0

T15

T16

T17

TIM1

T18

T19

T20

WDTOUT

T21

T22

T23

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-30 assumes testing over recommended operating conditions (see Figure 5-31).

Table 5-30. TIM0/TIM1/WDTOUT Interrupt Timing Requirements

(1) (2)

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

T15

tsu(TIM0L-COH)

Setup time, TIM0 low(3) before CLKOUT rising edge

T16

th(COH-TIM0L)

Hold time, TIM0 low(3) after CLKOUT rising edge

T17

tw(TIM0L)

Pulse width, TIM0 low(3)

T18

tsu(TIM1L-COH)

Setup time, TIM1 low(3) before CLKOUT rising edge

T19

th(COH-TIM1L)

Hold time, TIM1 low(3) after CLKOUT rising edge

T20

tw(TIM1L)

Pulse width, TIM1 low(3)

T21

tsu(WDTL-COH)

Setup time, WDTOUT low(3) before CLKOUT rising edge

T22

th(COH-WDTL)

Hold time, WDTOUT low(3) after CLKOUT rising edge

T23

tw(WDTL)

Pulse width, WDTOUT low(3)

(1)

In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as

CLKOUT.

(2)

P = (Divider1 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the fast peripheral domain at 1/2

the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.

(3)

An interrupt can be triggered by setting the timer pins high or low, depending on the setting of the TIN1INV bit in the GPIO Interrupt

Control Register (GPINT). Refer to the TMS320VC5501/5502 DSP Timers Reference Guide (literature number SPRU618) for more

information on the interrupt capability of the timer pins.

Figure 5-31. TIM0/TIM1/WDTOUT Interrupt Timings

Specifications

157

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