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5.10

External Interrupt and Interrupt Acknowledge (IACK) Timings

INTx, NMI

CLKOUT

IACK

(A ) The figure shows the case in which CLKOUT is programmed to show a system clock that is operating at the same frequency as the

CPU clock.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004

Table 5-19 and Table 5-20 assume testing over recommended operating conditions (see Figure 5-23 and

Figure 5-24).

Table 5-19. External Interrupt and Interrupt Acknowledge Timing Requirements

VC5502-200

VC5502-300

NO.

UNIT

MIN

MAX

tw(INTL)A

Pulse width, interrupt low, CPU active

3P(1)

tw(INTH)A

Pulse width, interrupt high, CPU active

1P(1)

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.

Table 5-20. External Interrupt and Interrupt Acknowledge Switching Characteristics

VC5502-200

VC5502-300

NO.

PARAMETER

UNIT

MIN

MAX

td(COH-IACKV)

Delay time, CLKOUT high to IACK valid(1)

(1)

In this case, CLKOUT refers to the CPU clock. Since CLKOUT cannot be programmed to reflect the CPU clock, there might be an extra

delay of a certain number of CPU clocks based on the ratio between the system clock shown on CLKOUT and the CPU clock. For

example, if SYSCLK2 is shown on CLKOUT and SYSCLK2 is programmed to be half the CPU clock, there might be an extra delay of

one CPU clock period between the transition of CLKOUT and the specified timing. If system clock is programmed to be one-fourth of the

CPU clock, there might be an extra delay of 1, 2, or 3 CPU clocks between the transition of CLKOUT and the specified timing. The extra

delay must be taken into account when considering the MAX value for the timing under question. Note that if the CPU clock and the

system clock shown on CLKOUT are operating at the same frequency, there will be no extra delay in the specified timing.

Figure 5-23. External Interrupt Timings

Figure 5-24. External Interrupt Acknowledge Timings

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Specifications

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