ADC32RF83 datasheet(114/138 Pages) TI

114 / 138 page

114

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: ADC32RF80 ADC32RF83

Submit Documentation Feedback

8.5.13.10 Register 01Dh-01Eh (address = 01Dh-01Eh), Power Detector Page

Figure 237. Register 01Dh

DWELLIIR[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 238. Register 01Eh

DWELLIIR[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 107. Register 01Dh-01Eh Field Descriptions

Bit

Field

Type

Reset

Description

7-0

DWELLIIR

R/W

DWELL time counter for the IIR output comparators. When the

IIR filter output crosses the upper thresholds FIL0THH or

FIL1THH, the IIR peak detector output flags are set. In order to

be reset, the output of the IIR filter must remain continuously

lower than the lower threshold (FIL0THL or FIL1THL) for the

period specified by the DWELLIIR value. This threshold is 16

bits and is specified in terms of fS / 8 clock cycles.

Example: if fS = 3 GSPS, fS / 8 = 375 MHz, and DWELLIIR =

0100h, then the DWELL time = 29 / 375 MHz = 1.36 µs.

8.5.13.11 Register 020h (address = 020h), Power Detector Page

Figure 239. Register 020h

RMSDET EN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 108. Register 020h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Must write 0

RMSDET EN

R/W

This bit enables the RMS power detector.

0 = Power detector disabled

1 = Power detector enabled

ADC32RF83 bảng dữ liệu(PDF) 114 Page - Texas Instruments

ADC32RF83 bảng dữ liệu(HTML) 114 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL