ADC32RF83 datasheet(52/138 Pages) TI

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Randomly

Pick 1 Out of

8 Samples

Output

of ADC

Accumulate

Over 2^M

Inputs

fS/8

M = [1..2

16]

>THHigh

>THLow

Hysteresis

-M

1 or 2-Bit

Mode

2-Bit Mode

10: High

00: Mid

01: Low

1-Bit Mode

With Hysteresis

1: High

0: Low

PWR DET

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

www.ti.com

Product Folder Links: ADC32RF80 ADC32RF83

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8.3.8.3 RMS Power Detector

In this detector mode the peak power is computed for a block of N samples over a programmable block length

and then compared against two sets of programmable thresholds (with hysteresis).

The RMS power detector circuit provides configuration options, as shown in Figure 129. The RMS power value

(1 or 2 bit) can be output onto the GPIO pins. In 2-bit output mode, two different thresholds are used whereas the

1-bit output provides one threshold together with hysteresis.

Figure 129. RMS Power Detector Implementation

Table 11 shows the register configurations required to set up the RMS power detector. The detector operates in

the fS / 8 clock domain. The AGC modes can be configured separately for channel A (54xxh) and channel B

(5Cxxh), although some registers are common in 54xxh (such as the GPIO pin selection).

Table 11. Registers Required for Using the RMS Power Detector Feature

ADDRESS

DESCRIPTION

RMSDET EN

5420h, 5C20h

Enables RMS detector

PWRDETACCU

5421h, 5C21h

Programs the block length to be used for RMS power computation. The block length

is defined in terms of fS / 8 clocks.

The block length can be programmed as 2M with M = 0 to 16.

PWRDETH,

PWRDETL

5422h, 5423h, 5424h,

5425h, 5C22h, 5C23h,

5C24h, 5C25h

The computed average power is compared against these high and low thresholds.

One LSB of the thresholds represents 1 / 216. For example: is PWRDETH is set to

–14 dBFS from peak, [10(–14 / 20)]2 × 216 = 2609, then set 5422h, 5423h, 5C22h,

5C23h = 0A31h.

RMS2BIT EN

5427h, 5C27h

Enables 2-bit output format for the RMS detector output.

OUTSEL GPIO[4:1]

5432h, 5433h,

5434h, 5435h

Connects the PWRDET alarms to the GPIO pins; common register.

IODIR

5437h

Selects the direction for the four GPIO pins; common register.

RESET AGC

542Bh, 5C2Bh

After configuration, reset the AGC module to start operation.

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