ADC32RF83 datasheet(11/138 Pages) TI

11 / 138 page

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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(1)

Overall latency = latency + tPD.

(2)

Latency increases when the DDC modes are used; see Table 5.

(3)

For latency in different DDC options, see .

(4)

Common-mode voltage for the SYSREF input is kept at 1.2 V.

6.10 Timing Requirements

typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient

temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed

performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless

otherwise noted)

MIN

NOM

MAX

UNIT

SAMPLE TIMING

Aperture delay

250

750

Aperture delay matching between two channels on the same device

±15

Aperture delay matching between two devices at the same

temperature and supply voltage

±150

Aperture jitter, clock amplitude = 2 VPP

Latency

(1) (2)

Data latency, ADC sample to

digital output

DDC block bypassed(3), LMFS = 8224

424

Input

clock

cycles

Fast overrange latency, ADC sample to FOVR indication on GPIO pins

tPD

Propagation delay time: logic gates and output buffer delay

(does not change with fS)

SYSREF TIMING(4)

tSU_SYSREF SYSREF setup time: referenced to clock rising edge, 2949.12 MSPS

140

tH_SYSREF

SYSREF hold time: referenced to clock rising edge, 2949.12 MSPS

Valid transition window sampling period: tSU_SYSREF – tH_SYSREF, 2949.12 MSPS

143

JESD OUTPUT INTERFACE TIMING

Unit interval: 12.5 Gbps

100

400

Serial output data rate

2.5

10.0

12.5

Gbps

Rise, fall times: 1-pF, single-ended load capacitance to ground

Total jitter: BER of 1E-15 and lane rate = 12.5 Gbps

%UI

Random jitter: BER of 1E-15 and lane rate = 12.5 Gbps

0.99

%UI, rms

Deterministic jitter: BER of 1E-15 and lane rate = 12.5 Gbps

9.1

%UI, pk-

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