ADC32RF83 datasheet(53/138 Pages) TI

53 / 138 page

JESD204B Long

Transport Layer

Test Pattern

Data Mapping

Frame

Construction

8b, 10b

Encoding

JESD204B

Link Layer

Test Pattern

Serializer

ADC Section

Transport Layer

Link Layer

PHY Layer

Interleaving

Engine

Digital Block

ADC

Scrambler

1 + x

14 + x15

12-bit

RAMP

Test

Patterns

Decimation

Filter Block

DDC

To GPIO

AGC Pins

OUTSEL GPIO[4:1]

IIR PK DET0 [2]

IIR PK DET1 [2]

BLKPKDETH [1]

BLKPKDETL [1]

FOVR

PWR DET [2]

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

Submit Documentation Feedback

8.3.8.4 GPIO AGC MUX

The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs for channel A and B.

The GPIO pins can be configured through the SPI control to output the alarm from the peak power (1 bit),

crossing detector (1 or 2 bit), faster overrange, or the RMS power output, as shown in Figure 130.

The programmable output MUX allows connecting any signal (including the NCO control) to any of the four GPIO

pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming.

Figure 130. GPIO Output MUX Implementation

8.3.9 Power-Down Mode

The ADC32RF8x provides a lot of configurability for the power-down mode. Power-down can be enabled using

the PDN pin or the SPI register writes.

8.3.10 ADC Test Pattern

The ADC32RF8x provides several different options to output test patterns instead of the actual output data of the

ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. The output

data path is shown in Figure 131.

Figure 131. Test Pattern Generator Implementation

8.3.10.1 Digital Block

The ADC test pattern replaces the actual output data of the ADC. The test patterns listed in Table 12 are

available when the DDC is enabled and located in register 37h of the decimation filter page. When programmed,

the test patterns are output for each converter (M) stream. The number of converter streams per channel

increases by 2 when complex (I, Q) output or dual-band DDC is selected. The test patterns can be synchronized

for both ADC channels using the SYSREF signal.

Additionally, a 12-bit test pattern is also available.

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