ADC32RF83 datasheet(91/138 Pages) TI

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ADC32RF80, ADC32RF83

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SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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8.5.11.2 Register 002h (address = 002h ), JESD Digital Page

Figure 172. Register 002h

SYNC REG

SYNC REG EN

12BIT MODE

JESD MODE0

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 60. Register 002h Field Descriptions

Bit

Field

Type

Reset

Description

SYNC REG

R/W

This bit provides SYNC control through the SPI.

0 = Normal operation

1 = ADC output data are replaced with K28.5 characters

SYNC REG EN

R/W

This bit is the enable bit for SYNC control through the SPI.

0 = Normal operation

1 = SYNC control through the SPI is enabled (ignores the

SYNCB input pins)

5-4

Must write 0

3-2

12BIT MODE

R/W

This bit enables the 12-bit output mode for more efficient data

packing.

00 = Normal operation, 14-bit output

01, 10 = Unused

11 = High-efficient data packing enabled

1-0

JESD MODE0

R/W

These bits select the configuration register to configure the

correct LMFS frame assemblies for different decimation settings;

see the JESD frame assembly tables in the JESD204B Frame

Assembly section.

00 = 0

01 = 1

10 = 2

11 = 3

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