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ADC32RF83 bảng dữ liệu(PDF) 81 Page - Texas Instruments

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tên linh kiện ADC32RF83
Giải thích chi tiết về linh kiện  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
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ADC32RF83 bảng dữ liệu(HTML) 81 Page - Texas Instruments

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ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.3.5 Register 05Ah (address = 05Ah), Master Page
Figure 156. Register 05Ah
7
6
5
4
3
2
1
0
SYSREF DEL[2:0]
0
0
0
0
0
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 42. Register 05Ah Field Descriptions
Bit
Field
Type
Reset
Description
7
SYSREF DEL2
W
0h
When the SYSREF delay feature is enabled (3Ch, bit 6) the
delay can be adjusted in 25-ps steps; the first step is 175 ps.
The PVT variation of each 25-ps step is ±10 ps. The 175-ps step
is ±50 ps; see Table 43.
6
SYSREF DEL1
R/W
5
SYSREF DEL0
W
4-0
0
W
0h
Must write 0
Table 43. SYSREF DEL[2:0] Bit Settings
STEP
SETTING
STEP (NOM)
TOTAL DELAY (NOM)
1
01000
175 ps
175 ps
2
00111
25 ps
200 ps
3
00110
25 ps
225 ps
4
00101
25 ps
250 ps
5
00100
25 ps
275 ps
6
00011
25 ps
300 ps
8.5.3.6 Register 03Dh (address = 3Dh), Master Page
Figure 157. Register 03Dh
7
6
5
4
3
2
1
0
0
0
0
0
0
JESD OUTPUT SWING
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 44. Register 03Dh Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
2-0
JESD OUTPUT SWING
R/W
0h
These bits select the output amplitude, VOD (mVPP), of the JESD
transmitter for all lanes.
0 = 860 mVPP
1= 810 mVPP
2 = 770 mVPP
3 = 745 mVPP
4 = 960 mVPP
5 = 930 mVPP
6 = 905 mVPP
7 = 880 mVPP



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