ADC32RF83 datasheet(86/138 Pages) TI

86 / 138 page

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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8.5.7 Offset Corr Page Channel B (610000h, M = 1)

8.5.7.1 Register 068h (address = 068h), Offset Corr Page Channel B

Figure 165. Register 068h

FREEZE OFFSET

CORR

ALWAYS WRITE 1

DIS

OFFSET

CORR

ALWAYS WRITE 1

R/W-0h

W-0h

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 53. Register 068h Field Descriptions

Bit

Field

Type

Reset

Description

7,5,1

FREEZE OFFSET CORR

R/W

Use this bit and bits 5 and 1 to freeze the offset estimation

process of the offset corrector; see the Using DC Coupling in

the ADC32RF8x section.

011 = Apply this setting after powering up the device

111 = Offset corrector is frozen, does not estimate offset

anymore, and applies the last computed value.

Others = Do not use

Must write 0

ALWAYS WRITE 1

R/W

Always write this bit as 1 for the offset correction block to work

properly.

4-3

Must write 0

DIS OFFSET CORR

R/W

0 = Offset correction block works and removes fS / 8, fS / 4,

3fS / 8, and fS / 2 spurs

1 = Offset correction block is disabled

ALWAYS WRITE 1

R/W

Always write this bit as 1 for the offset correction block to work

properly.

Must write 0

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