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ADC32RF83 bảng dữ liệu(PDF) 88 Page - Texas Instruments

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tên linh kiện ADC32RF83
Giải thích chi tiết về linh kiện  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
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ADC32RF83 bảng dữ liệu(HTML) 88 Page - Texas Instruments

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.9.2 Register 0A2h (address = 0A2h), Main Digital Page Channel A
Figure 168. Register 0A2h
7
6
5
4
3
2
1
0
0
0
0
0
NQ ZONE EN
NYQUIST ZONE
W-0h
W-0h
W-0h
W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 56. Register 0A2h Field Descriptions
Bit
Field
Type
Reset
Description
7-4
0
W
0h
Must write 0
3
NQ ZONE EN
R/W
0h
This bit allows for specification of the operating Nyquist zone.
0 = Nyquist zone specification disabled
1 = Nyquist zone specification enabled
2-0
NYQUIST ZONE
R/W
0h
These bits specify the operating Nyquist zone for the analog
correction loop.
Set the NQ ZONE EN bit before programming these bits.
For example, at s 3-GSPS chip clock, the first Nyquist zone is
from dc to 1.5 GHz, the second Nyquist zone is from 1.5 GHz to
3 GHz, and so on.
000 = First Nyquist zone (dc – fS / 2)
001 = Second Nyquist zone (fS / 2 – fS)
010 = Third Nyquist zone
011 = Fourth Nyquist zone
8.5.10 Main Digital Page Channel B (680001h, M = 1)
8.5.10.1 Register 000h (address = 000h), Main Digital Page Channel B
Figure 169. Register 000h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DIG CORE RESET GBL
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 57. Register 000h Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
W
0h
Must write 0
0
DIG CORE RESET GBL
R/W
0h
Pulse this bit (0
→1 →0) to reset the digital core (applies to both
channel A and B).
All Nyquist zone settings take effect when this bit is pulsed.



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