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ADC32RF83 bảng dữ liệu(PDF) 83 Page - Texas Instruments

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tên linh kiện ADC32RF83
Giải thích chi tiết về linh kiện  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
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ADC32RF83 bảng dữ liệu(HTML) 83 Page - Texas Instruments

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ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.4 ADC Page (FFh, M = 0)
8.5.4.1 Register 03Fh (address = 03Fh), ADC Page
Figure 160. Register 03Fh
7
6
5
4
3
2
1
0
0
0
0
0
0
SLOW SP EN1
0
0
W-0h
W-0h
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 47. Register 03Fh Field Descriptions
Bit
Field
Type
Reset
Description
7-3
0
W
0h
Must write 0
2
SLOW SP EN1
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
1-0
0
W
0h
Must write 0
8.5.4.2 Register 042h (address = 042h), ADC Page
Figure 161. Register 042h
7
6
5
4
3
2
1
0
0
0
0
SLOW SP EN2
0
0
0
0
W-0h
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 48. Register 042h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4
SLOW SP EN2
R/W
0h
This bit must be enabled for clock rates below 2.5 GSPS.
0 = ADC sampling rates are faster than 2.5 GSPS
1 = ADC sampling rates are slower than 2.5 GSPS
3-0
0
W
0h
Must write 0



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