ADC32RF83 datasheet(75/138 Pages) TI

75 / 138 page

ADC32RF80, ADC32RF83

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SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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8.5.1 Example Register Writes

This section provides three different example register writes. Table 28 describes a global power-down register

write, Table 29 describes the register writes when the scrambler is enabled, and Table 30 describes the register

writes for 8X decimation for channels A and B (complex output, 1 DDC mode) with the NCO set to 1.8 GHz (fS =

3 GSPS) and the JESD format configured to LMFS = 4421.

Table 28. Global Power-Down

ADDRESS

DATA

COMMENT

12h

04h

Set the master page

20h

01h

Set the global power-down

Table 29. Scrambler Enable

ADDRESS

DATA

COMMENT

4004h

69h

Select the digital JESD page

4003h

00h

6006h

80h

Scrambler enable, channel A

7006h

80h

Scrambler enable, channel B

Table 30. 8X Decimation for Channel A and B

ADDRESS

DATA

COMMENT

4004h

68h

Select the main digital page for channel A

4003h

00h

6000h

01h

Issue a digital reset for channel A

6000h

00h

Clear the digital for reset channel A

4003h

01h

Select the main digital page for channel B

6000h

01h

Issue a digital reset for channel B

6000h

00h

Clear the digital reset for channel B

4004h

69h

Select the digital JESD page

4003h

00h

6002h

01h

Set JESD MODE0 = 1, channel A

7002h

01h

Set JESD MODE0 = 1, channel B

5000h

01h

Enable the DDC, channel A

5001h

02h

Set decimation to 8X complex

5007h

9Ah

Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.8 GHz, fS = 3 GSPS)

5008h

99h

Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.8 GHz, fS = 3 GSPS)

5014h

01h

Enable the 6-dB digital gain of DDC0

5801h

02h

Set decimation to 8X complex

5807h

9Ah

Set the LSB of DDC0, NCO1 to 9Ah (fNCO = 1.8 GHz, fS = 3 GSPS)

5808h

99h

Set the MSB of DDC0, NCO1 to 99h (fNCO = 1.8 GHz, fS = 3 GSPS)

5814h

01h

Enable the 6-dB digital gain of DDC0

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