ADC32RF83 datasheet(90/138 Pages) TI

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ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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8.5.11 JESD Digital Page (6900h, M = 1)

8.5.11.1 Register 001h (address = 001h), JESD Digital Page

Figure 171. Register 001h

CTRL K

TESTMODE EN

LANE ALIGN

FRAME ALIGN

TX LINK DIS

R/W-0h

W-0h

R/W-0h

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 59. Register 001h Field Descriptions

Bit

Field

Type

Reset

Description

CTRL K

R/W

This bit is the enable bit for the number of frames per

multiframe.

0 = Default is five frames per multiframe

1 = Frames per multiframe can be set in register 06h

6-5

R/W

Must write 0

TESTMODE EN

This bit generates a long transport layer test pattern mode

according to section 5.1.6.3 of the JESD204B specification.

0 = Test mode disabled

1 = Test mode enabled

Must write 0

LANE ALIGN

R/W

This bit inserts a lane alignment character (K28.3) for the

receiver to align to the lane boundary per section 5.3.3.5 of the

JESD204B specification.

0 = Normal operation

1 = Inserts lane alignment characters

FRAME ALIGN

R/W

This bit inserts a frame alignment character (K28.7) for the

receiver to align to the frame boundary per section 5.3.35 of the

JESD204B specification.

0 = Normal operation

1 = Inserts frame alignment characters

TX LINK DIS

R/W

This bit disables sending the initial link alignment (ILA) sequence

when SYNC is deasserted.

0 = Normal operation

1 = ILA disabled

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