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ADC32RF83 bảng dữ liệu(PDF) 93 Page - Texas Instruments

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tên linh kiện ADC32RF83
Giải thích chi tiết về linh kiện  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
PDF  138 Pages
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Trang chủ  http://www.ti.com
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ADC32RF83 bảng dữ liệu(HTML) 93 Page - Texas Instruments

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ADC32RF80, ADC32RF83
www.ti.com
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.11.5 Register 006h (address = 006h), JESD Digital Page
Figure 175. Register 006h
7
6
5
4
3
2
1
0
SCRAMBLE EN
0
0
0
0
0
0
0
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 63. Register 006h Field Descriptions
Bit
Field
Type
Reset
Description
7
SCRAMBLE EN
R/W
0h
This bit is the scramble enable bit in the JESD204B interface.
0 = Scrambling disabled
1 = Scrambling enabled
6-0
0
W
0h
Must write 0
8.5.11.6 Register 007h (address = 007h), JESD Digital Page
Figure 176. Register 007h
7
6
5
4
3
2
1
0
0
0
0
FRAMES PER MULTIFRAME (K)
W-0h
W-0h
W-0h
R/W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 64. Register 007h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4-0
FRAMES PER MULTIFRAME (K)
R/W
0h
These bits set the number of multiframes.
Actual K is the value in hex + 1 (that is, 0Fh is K = 16).
8.5.11.7 Register 016h (address = 016h), JESD Digital Page
Figure 177. Register 016h
7
6
5
4
3
2
1
0
0
40x MODE
0
0
0
0
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 65. Register 016h Field Descriptions
Bit
Field
Type
Reset
Description
7
0
W
0h
Must write 0
6-4
40x MODE
R/W
0h
This register must be set for 40X mode operation.
000 = Register is set for 20X and 80X mode
111 = Register must be set for 40X mode
3-0
0
W
0h
Must write 0



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