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ADC32RF83 bảng dữ liệu(PDF) 82 Page - Texas Instruments

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tên linh kiện ADC32RF83
Giải thích chi tiết về linh kiện  ADC32RF8x Dual-Channel, 3-GSPS Telecom Receiver and Feedback Devices
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ADC32RF83 bảng dữ liệu(HTML) 82 Page - Texas Instruments

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ADC32RF80, ADC32RF83
SBAS774A – MAY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADC32RF80 ADC32RF83
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
8.5.3.7 Register 057h (address = 057h), Master Page
Figure 158. Register 057h
7
6
5
4
3
2
1
0
0
0
0
SEL SYSREF REG
ASSERT SYSREF REG
0
0
0
W-0h
W-0h
W-0h
R/W-0h
R/W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 45. Register 057h Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
W
0h
Must write 0
4
SEL SYSREF REG
R/W
0h
SYSREF can be asserted using this bit. Ensure that the SEL
SYSREF REG register bit is set high before using this bit; see
Using SYSREF .
0 = SYSREF is logic low
1 = SYSREF is logic high
3
ASSERT SYSREF REG
R/W
0h
Set this bit to use the SPI register to assert SYSREF.
0 = SYSREF is asserted by device pins
1 = SYSREF can be asserted by the ASSERT SYSREF REG
register bit
Other bits = 0
2-0
0
W
0h
Must write 0
8.5.3.8 Register 058h (address = 058h), Master Page
Figure 159. Register 058h
7
6
5
4
3
2
1
0
0
0
SYNCB POL
0
0
0
0
0
W-0h
W-0h
R/W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset
Table 46. Register 058h Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
W
0h
Must write 0
5
SYNCB POL
R/W
0h
This bit inverts the SYNCB polarity.
0 = Polarity is not inverted; this setting matches the timing
diagrams in this document and is the proper setting to use
1 = Polarity is inverted
4-0
0
W
0h
Must write 0



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