ADC32RF83 datasheet(105/138 Pages) TI

105 / 138 page

105

ADC32RF80, ADC32RF83

www.ti.com

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

Product Folder Links: ADC32RF80 ADC32RF83

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8.5.12.20 Register 01Fh (address = 01Fh), Decimation Filter Page

Figure 206. Register 01Fh

WBF 6DB GAIN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 92. Register 01Fh Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Must write 0

WBF 6DB GAIN

R/W

This bit scales the output of the wide bandwidth DDC filter by 2

(6 dB) to compensate for real-to-complex conversion and image

suppression. This setting only applies to the high-bandwidth filter

path (divide-by-4 and -6).

0 = Normal operation

1 = 6-dB digital gain is added

8.5.12.21 Register 033h-036h (address = 033h-036h), Decimation Filter Page

Figure 207. Register 033h

CUSTOM PATTERN1[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 208. Register 034h

CUSTOM PATTERN1[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 209. Register 035h

CUSTOM PATTERN2[7:0]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Figure 210. Register 036h

CUSTOM PATTERN2[15:8]

R/W-0h

LEGEND: R/W = Read/Write; -n = value after reset

Table 93. Register 033h-036h Field Descriptions

Bit

Field

Type

Reset

Description

7-0

CUSTOM PATTERN

R/W

These bits set the custom test pattern in address 33h, 34h, 35h,

or 36h.

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