ADC32RF83 datasheet(104/138 Pages) TI

104 / 138 page

104

ADC32RF80, ADC32RF83

SBAS774A – MAY 2016 – REVISED DECEMBER 2016

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Product Folder Links: ADC32RF80 ADC32RF83

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8.5.12.18 Register 016h (address = 016h), Decimation Filter Page

Figure 204. Register 016h

DDC1 6DB GAIN

W-0h

R/W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 89. Register 016h Field Descriptions

Bit

Field

Type

Reset

Description

7-1

Must write 0

DDC1 6DB GAIN

R/W

This bit scales the output of DDC1 by 2 (6 dB) to compensate

for real-to-complex conversion and image suppression. This

scaling does not apply to the high-bandwidth filter path (divide-

by-4 and -6); see register 1Fh.

0 = Normal operation

1 = 6-dB digital gain is added

8.5.12.19 Register 01Eh (address = 01Eh), Decimation Filter Page

Figure 205. Register 01Eh

DDC DET LAT

W-0h

R/W-0h

W-0h

LEGEND: R/W = Read/Write; W = Write only; -n = value after reset

Table 90. Register 01Eh Field Descriptions

Bit

Field

Type

Reset

Description

Must write 0

6-4

DDC DET LAT

R/W

These bits ensure deterministic latency depending on the decimation setting

used; see Table 91.

3-0

Must write 0

Table 91. DDC DET LAT Bit Settings

SETTING

COMPLEX DECIMATION SETTING

10h

Divide-by-24, -32 complex

20h

Divide-by-16, -18, -20 complex

40h

Divide-by-by 6, -12 complex

50h

Divide-by-4, -8, -9, -10 complex

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